Fabricating smaller, more densely packed devices having greater computing capability is a continuing objective in building semiconductor devices. In designing semiconductor devices, each cell of the device requires power input (Vdd) and ground (Vss) connections. To power the various components, each cell is also coupled to a power rail which is electrically connected to an active layer of the cell to provide the input power (Vdd). In some instances, a plurality of power rails may be provided for each cell to respectively provide the input power (Vdd) and the ground (Vss).
To improve area scaling as pitch scaling slows, track count of the standard cell libraries can be reduced, and architecture reset. However, track reduction beyond 6T (6 tracks) is difficult due to a lack of signal tracks available for automated routing. Also, due to lithographic overlay tolerances, it becomes difficult to consider to bury the power rail in smaller technology nodes so as to reduce track count, without shorting of the devices.